1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including, as its components, insulated gate type field effect transistors having different gate insulating film thicknesses. More specifically, the present invention relates to a DRAM (Dynamic Random Accesses Memory) cell-based semiconductor memory device.
2. Description of the Background Art
A DRAM cell is formed of a capacitor for storing information in the form of electric charges, and a transistor for accessing the capacitor. A semiconductor memory device (hereinafter, representatively referred to as “DRAM”) using such a one-transistor/one-capacitor type DRAM cell is utilized in a wide variety of fields covering a main memory for a computer and a working memory for portable equipment because of its small cell-occupation area and excellent cost-competitiveness owing to advanced miniaturization technology. A server and others utilize a large number of DRAMs. Also, the DRAM is utilized in applications employing a battery as a power source. Thus, there has been a requirement for reduction in power consumption in these applications and therefore, a power supply potential supplied externally has been reduced down to 1.8 V or below.
Conventionally, in match with reduction of an external power supply voltage, a design rule including a gate insulating film thickness Tox of a MOS transistor (insulated gate type field effect transistor) has been scaled down, thereby shrinking a size of such MOS transistor. In a conventional approach, all MOS transistors constituting a DRAM have the same gate insulating film thickness Tox.
However, under the condition of an external power supply voltage being below 1.8 V, there may be a situation where the conventional method can not be utilized. More specifically, for the circuitry which operates on a potential lower than the external power supply voltage, such as a peripheral circuit and a sense amplifier in a memory array, a MOS transistor is required to have a thinner gate insulating film in view of a lower threshold voltage and a higher current driving power. On the other hand, for a memory cell transistor which is supplied with a boosted potential, it is difficult to employ a MOS transistor having the same gate insulating film as that of the MOS transistor in the peripheral circuit, in view of the breakdown voltage of the gate insulating film. On the contrary, if a single type of MOS transistors having a thicker gate insulating film that can ensure the breakdown voltage of the memory cell transistor is employed for the whole of the constituent elements, the threshold voltage increases in absolute value, thereby making it difficult to meet the specification values required in terms of an operation speed.
Therefore, as described in Prior Art Document 1 (Japanese Patent Laying-Open No. 2001-68634), it has been proposed to selectively use a gate insulating film of a MOS transistor according to operation characteristics or the operation potential required for each circuit. A circuit which is supplied with a boosted potential, such as a memory cell transistor, is formed of a MOS transistor having a large gate insulating film thickness Tox1. On the other hand, a circuit which operates on a lower potential than the external power supply potential, such as a peripheral circuit or a sense amplifier, is formed of a MOS transistor having a thinner gate insulating film of a film thickness of Tox2. Such a structure in which MOS transistors having different kinds of gate insulating films are formed is achieved through a “dual oxide” process and is utilized in a system LSI having a logic and a DRAM integrated on a common chip. In the dual oxide process, a MOS transistor having a thick gate insulating film (hereinafter, referred to as “thick film MOS transistor”) and a MOS transistor with a thin gate insulating film (hereinafter, referred to as “thin film MOS transistor”) are formed in the same process steps, and subsequently the gate insulating film of the thin film MOS transistor is thinned (or all removed) with the thick film MOS transistor masked by a resist. Then, the gate insulating films of the thick film MOS transistor and the thin film MOS transistor are thickened again, through the same process step(s).
Prior Art Document 1 describes, as a conventional art of a semiconductor integrated circuit device having a logic and a DRAM mixedly assembled, the construction in which a peripheral circuit and an in-array circuit of a DRAM core are formed of thick film transistors. In the conventional technique described in Prior Art Document 1, adjustment of an absolute value of a threshold voltage is performed through ion implantation. In order to resolve the problem of an increase in the number of process steps and in the number of masks resulting from the threshold voltage adjustment through ion implantation in the conventional technique, in Prior Art Document 1, a sense amplifier and a column selection gate are formed of thin film transistors and bit line peripheral circuitry, such as a bit line precharging/equalizing circuit and a bit line isolation gate, are formed of thick film MOS transistors, and peripheral circuitry such as a control circuit is formed of thin film MOS transistors.
Further, according to Prior Art Document 1, a thick film MOS transistors having a thick gate insulating film is employed for a memory cell transistor and a word line driving circuit section in a row selection circuit. A circuit for generating an internal power supply voltage performs an analog operation (a current mirror operation and a source follower mode operation) and in this circuit, a thick film MOS transistor having a threshold voltage of a large absolute value is employed in order to suppress influence of off-leakage current to ensure an accurate internal voltage generating operation.
In a column-related circuit and a control circuit in the peripheral circuitry, thin film MOS transistors are employed. A column decoder and a preamplifier/write driver are column-related circuits which operate in a column selecting operation and the number of the column decoders and the preamplifier/writing drivers are small as compared with the number of the circuits related to row selection that are provided in a memory array and the number of unit decode circuits included in a row decoder. Therefore, even if thin film MOS transistors are employed in these column-related circuits, generated off-leakage currents are sufficiently small, thus suppressing the influence on an increase in current consumption in a standby state. On the other hand, by employing thin film MOS transistors in the column-related circuit and the control circuit, these column-related circuit and control circuit operate at high speed even under a condition of low power supply voltage, achieving high speed column access and high speed internal operation.
A sense amplifier circuit placed in a sense amplifier band is formed of thin film MOS transistors, and the necessity of an ion implantation process for threshold voltage adjustment is eliminated. Since the absolute value of the threshold voltage is small and thus the driving power is large, the sense amplifier circuit can be operated at high speed even with a voltage (sense power supply voltage) lower than the external power supply voltage. Further, a column selection gate is formed of a thin film MOS transistor to improve the speed of data transfer with the outside of the memory array.
For the bit line isolation gate and the bit line precharge/equalize circuit, thick film MOS transistors are employed. The bit line isolation gate is supplied with a bit line isolation instruction signal at a high voltage level higher than the array power supply voltage (sense power supply voltage). Therefore, the breakdown characteristics is ensured. The bit line equalizing circuit is provided for each pair of bit lines and is coupled to the sense amplifier circuit through the bit line isolation gate. A bit line equalizing instruction signal is set to the voltage level higher than the array power supply voltage in order to transfer the precharge voltage at high speed. Therefore, the bit line equalizing circuit is formed of a thick film MOS transistor to ensure the breakdown immunity thereof.
In the structure described in Prior Art Document 1, MOS transistors having different gate insulating films are selectively placed according to operation characteristics required for each circuit using the dual oxide process, to achieve appropriate electric characteristics for the respective circuits.
Prior to shipment, the DRAM is subject to the burn-in for testing its reliability by applying high voltage stress to memory cells. There are some kinds of burn-in tests. In Prior Art Document 1, in order to avoid degradation of the reliability of the sense amplifier circuit and the column selection gate circuit formed of thin film MOS transistors due to the high voltage applied during a burn-in test, the high voltage is applied to the memory cells through the bit line equalizing circuits. In this state, the bit line isolation gate is set to a non-conductive state to isolate the bit lines from the sense amplifier circuit and the column selection gate circuit. This prevents the high voltage during the burn-in test from being applied to the thin film MOS transistors in the sense amplifier circuit and the column selection gate circuit.
In a static burn-in mode, all word lines are driven to the selected state, and word lines are supplied with such a boosted potential that allows the potential at a storage node (one-side electrode of the memory capacitor) for storing memory cell data to be set to a sufficiently high voltage level by a high potential applied from the bit line, and allows an appropriate voltage stress to be applied across the gate insulating film of the memory cell transistor. With this static burn-in test, voltage stress required for ensuring the reliability of the memory cells can be applied in a short time period.
However, as described in Prior Art Document 1, in the case of the use of the bit line equalizing circuit for applying voltage stress, the storage nodes of all memory cells are forced to the same voltage level. According to the burn-in voltage applying method, sufficient voltage stress can be applied to a dielectric film between the storage node and a cell plate node of the memory cell capacitor. However, with this method, no voltage stress is applied to an interlayer insulating film between the storage nodes of memory cell capacitors adjacent to each other in the word line direction. In order to apply voltage stress to the interlayer insulating film between the capacitors of memory cells adjacent to each other in the direction perpendicular to the bit line, or between the capacitor of the memory cell connected to a bit line BL and the capacitor of the memory cell connected to a complementary bit line ZBL, it may be possible to write the ground voltage into the storage nodes of all the memory cells first, then to drive the word lines for the memory cells connected to bit lines BL or ZBL to the selected state, and then to apply the boosted potential through the bit line equalizing circuits. In this case, the boosted voltage is applied to both bit lines BL and ZBL, and therefore the boosted voltage is applied to a bit line to which the boosted voltage does not need to be applied, and thus there causes unnecessary power consumption. Furthermore, this case impedes the advantage of the static burn-in test that all the word lines are driven to the selected state at the same time to shorten the testing time period.
It may be possible to provide a burn-in equalizing transistor dedicated to the static burn-in test for each bit line, instead of utilizing the bit line equalizing circuit. With the dedicated transistors for the burn-in provided on the respective bit lines BL and ZBL, one transfers the boosted voltage and the other transfers the ground voltage so that the boosted voltage can be applied to one of bit lines BL and ZBL and the ground voltage can be applied to the other of the bit lines BL and ZBL. Thus, a voltage can be applied to a dielectric film of a memory cell capacitor and also voltage stress can be applied to an interlayer insulating film between the storage nodes of adjacent memory cells. However, providing such dedicated burn-in equalizing circuits on the respective bit lines increases the area occupied by the bit line peripheral circuits and requires interconnection for transferring the boosted voltage for the burn-in test, resulting in an increased interconnection layout area.
Furthermore, in the case where both thick film MOS transistors and thin film MOS transistors are provided in a mixed manner in the sense amplifier band, some isolation regions are required, as will be described later. The dual gate process requires etching away of the gate insulating film of thin film MOS transistor once in forming the thick film MOS transistor and the thin film MOS transistor. Further, the dual gate process requires the ensured margin for the accuracy of the etching mask alignment. Further, it becomes necessary to relax the steps due to thickness differences between the gate insulating films of MOS transistors, which requires separation regions for relaxing the steps between the regions in which thin film MOS transistor are formed and the regions in which thick film MOS transistor are formed. By placing the separating regions for relaxing the steps, it is possible to accurately form resist patterns without being affected by halation of exposure light and others in patterning and also to prevent over-etching due to reflection of irradiated ions. Consequently, because of the separation region provided taking into account such mask alignment and process margin, there may arise such a problem that the layout area of the circuit in the sense amplifier band is increased and accordingly the array area is increased.